1 Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly relates to an effective technique in application to a semiconductor device including a MISFET having a sidewall structure and a method for fabricating the semiconductor device.
2. Description of Prior Art
As a field-effect transistor mounted in a semiconductor device, an insulating gate type field-effect transistor called MISFET (metal insulator semiconductor field-effect transistor) has been known. This type of MISFETs is characterized in that the degree of integration can be easily increased, and therefore has been widely used as a circuit element constituting an integrated circuit to contribute to acceleration recent reduction in device size. However, with reduction in device size, different kinds of problems regarding MISFETs have come to the surface. One of the problems is stress applied to a channel formation region in a MISFET. In an ultra-fine CMIS (complementary MIS) process with a gate length of 0.1 μm or less, device temperature has been reduced more and more for the purpose of introduction of new materials, suppression of a short channel effect in MISFETs and the like. With a reduced temperature, a residual stress tends to remain in a device. A residual stress resulting from process is applied to a surface layer portion in an active region of a semiconductor substrate, i.e., a channel formation region of a MISFET.
As for change in transistor characteristics with respect to a stress applied to a channel formation region, when a stress is applied in the same direction as the direction (gate length direction) in which a drain current (Id) flows, the followings have been known.    (1) A drain current of an n-channel MISFET (which will be herein referred to as an “nMISFET”) is reduced due to a compressive stress and is increased due to a tensile stress.    (2) A drain current of a p-channel MISFET (which will be herein referred to as a “pMISFET”) is increased due to a compressive stress and is reduced due to a tensile stress.Therefore, in recent years, techniques for intentionally utilizing a stress applied to a channel formation region to improve a driving power of a transistor have drawn attention.
For example, there has been proposed a method in which after formation of MISFETs, as silicon nitride films for a self aligning contact which also serve as interlevel insulating films (and which will be hereafter referred to as “liner nitride films”), a nitride film (tensile stress film) 107 for generating a tensile stress in a channel formation region is selectively formed, as shown in FIG. 17A, in an nMISFET region and a nitride film (compressive stress film) 108 for generating a compressive stress in a channel formation region is selectively formed, as shown in FIG. 17B, in a pMISFET, so that a driving power of each of the MISFETs is improved (see Non-patent reference 1). In each of FIGS. 17A and 17B, 100 denotes a semiconductor substrate, 101 denotes a gate insulating film, 102 denotes a gate electrode, 103 denotes an extension region, 104 denotes insulating sidewalls, 105 denotes source/drain regions, and 106 denotes a silicide layer. As shown in FIGS. 17A and 17B, the tensile stress film 107 itself shrinks and the compressive stress film 108 itself expands.
It has been known that the larger a thickness of each of a tensile stress film and a compressive stress film is, the larger a stress generated in a channel region becomes. Therefore, a tensile stress film having an increased thickness and a compressive stress film having an increased thickness can improve respective driving powers of an nMISFET and a pMISFET.
(Patent Reference 1)
Japanese Laid-Open Publication No. 2003-273240
(Non-Patent Reference 1)
S. Pidin, et al., CMOS Architecture using Tensile and Compressive Nitride Films, Semiconductor/Integrated Circuit Technology 68th Symposium Lecture Memoir, pp. 19-22, 2005